Version 0.1

4-bit
Boots from flash
4kB
Registers:
	acc
	b
	ar0
	ar1
	ar2

nop		Delay a cycle.

apsh	Pushes the address register into the address register stack.

lda		Load the accumulator from an address pointed to by the address register.
ldi	#	Load ar0 with a number.

mov # #	Swap the contents of the accumulator with the contents of another register.

add	r	Add two registers together and store in the accumulator.
sub	r	Subtract two registers together and store in the accumulator.
and	r	AND two registers together and store in the accumulator.
or r	OR two registers together and store in the accumulator.
xor	r	XOR two registers together and store in the accumulator.
cmp	r	Subtract two registers together.

shr		Shift the accumulator right.

push r	Push a stack register onto the stack.

pop	r	Pop a stack register off of the stack.

st		Store the accumulator into the address pointed to by the address register.
br #	Branch to the address stored in the address register depending on the condition codes.


Standard Registers:
0	Acc	Accumulator
1	PC	Program Counter
2	AR0	Address Register 0
3	SP	Stack Pointer

Stack Registers:
0	Acc	Accumulator
1	PC	Program Counter
2	AR1	Address Register 1
3	AR2	Address Register 2

nop
	mem[pc++]->ir
	nop?
	
apsh
	mem[pc++]->ir
	ar0->ar1->ar2
	
lda
	mem[pc++]->ir
	mem[ar]->acc
	
ldi #
	mem[pc++]->ir
	mem[pc++]->acc
	
@mov # #
	mem[pc++]->ir
	reg[mem[pc][3:2]]->reg[mem[pc][1:0]];pc++
	
add r
	mem[pc++]->ir
	reg[mem[pc++][1:0]]+acc+cf->acc
	
sub r
	mem[pc++]->ir
	acc-reg[mem[pc++][1:0]]-cf->acc
	
and r
	mem[pc++]->ir
	reg[mem[pc++][1:0]]&acc->acc
	
or r
	mem[pc++]->ir
	reg[mem[pc++][1:0]]|acc->acc
	
xor r
	mem[pc++]->ir
	reg[mem[pc++][1:0]]^acc->acc
	
sub r
	mem[pc++]->ir
	acc-reg[mem[pc++][1:0]]-cf
	
shr
	mem[pc++]->ir
	{sf,acc[3:1]}->acc
	
@push
	mem[pc++]->ir
	acc->mem[sp--]
	
@pop
	mem[pc++]->ir
	mem[sp++]->acc
	
st
	mem[pc++]->ir
	acc->mem[ar]
	
br #
	mem[pc++]->ir
	&(cc^flags)?ar:pc->pc

Flags:	
c
s
v
z

Parts:
01	Flash - Program memory
02	RAM - Program/data memory
03	74574 - Output
04	74574 - Input
05	74381 - ALU
06	74574 - Accumulator
07	74*7* - Address register 0
08	74244 - Address register 0 and Accumulator output
09	74*7* - Address register 1 and 2
10	74244 - Address register 1 and 2 output
11	74163 - Program counter low
12	74163 - Program counter medium
13	74163 - Program counter high
14	74*** - Stack pointer low
15	74*** - Stack pointer high
16	74*7* - Flag register
17	74244 - Flag register and ALU output
17	74*7* - Instruction register
18	74163 - Microprogram counter
19	Flash - Microcode
20	Flash - Microcode

Version 0.2

add
sub
cmp
xor
or
and

ldi
lda

st

br

nop



0	pcl
1	pcm
2	pch
3	spl?
4	spm?
5	sph?
6	arl
7	arm
8	arh
9	acca
a	accb?
b	fr?
c	
d	
e	
f	

0:
pcl
pcm
pch

1:
spl
spm
sph

2:
arl
arm
arh

3:
acca
accb
fr

Final instruction set:
0	add		acc + b -> acc
1	sub		acc - b -> acc
2	cmp		acc - b
3	and		acc & b -> acc
4	or		acc | b -> acc
5	xor		acc ^ b -> acc
6	ldi		mem[pc] -> b
7	ld		mem[ar] -> b
8	st		acc -> mem[ar]
9	nop		
a	br		&(cc ^ fr) ? ar : pc -> pc
b	shr		acc >> 1 -> acc
c	swf		acc -> fr; fr -> acc
d	mov		acc -> b
e	swp		acc -> b; b -> acc
f	psh		b -> ar0; ar0 -> ar1; ar1 -> ar2

Instruction groups:
	Arithmetic group:
3		add
2		sub
1		cmp
6		and
5		or
4		xor
7		shr
	Load group:
9		ldi #
8		ld
	Swap group:
a		swp
b		swf
	Other group:
0		st
f		nop
d		br #
c		mov
e		psh

Register transfer description:
0	st
	mem[pc++] -> ir
	acc -> mem[ar]
	
1	cmp
	mem[pc++] -> ir
	acc - b; modify flags
	
2	sub
	mem[pc++] -> ir
	acc - b -> acc; modify flags
	
3	add
	mem[pc++] -> ir
	acc + b -> acc; modify flags
	
4	xor
	mem[pc++] -> ir
	acc ^ b -> acc; modify flags
	
5	or
	mem[pc++] -> ir
	acc | b -> acc; modify flags
	
6	and
	mem[pc++] -> ir
	acc & b -> acc; modify flags
	
7	shr
	mem[pc++] -> ir
	acc >> 1 -> acc; modify flags
	
8	ld
	mem[pc++] -> ir
	mem[ar] -> b
	
9	ldi #
	mem[pc++] -> ir
	mem[pc] -> b
	
a	swp?
	mem[pc++] -> ir
	b -> t
	acc -> b
	t -> acc
	
b	swf
	mem[pc++] -> ir
	fr -> t
	acc -> fr
	t -> acc
	
c	mov
	mem[pc++] -> ir
	acc -> b
	
d	br #
	mem[pc++] -> ir
	(mem[pc][2] ^ cc[mem[pc][1:0]]) ? ar : pc + 1 -> pc;
	
e	psh
	mem[pc++] -> ir
	b -> ar0; ar0 -> ar1; ar1 -> ar2
	
f	nop
	mem[pc++] -> ir


Macro types:

Letter: address of a memory location.
Number: a 4-bit constant.

Macros:
*ldi a #
*mov b a
nop
*jmp ####
*not a
*neg a
*inc a
*dec a
*addi a #
*subi a #
*andi a #
*ori a #
*xori a #
%getf
%putf
*xnori a #
*cmpi a #
*test a
	*ijmp [a, a+1, a+2, a+3]
	*add b a
	*sub b a
	*and b a
	*or b a
	*xor b a
	*xnor b a
	*ld b a
	*st b a
	*imov b a

*Memory-memory operations
%Memory-register operations

ldi a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LDI #			//Load '#'.
	ST				//Store '#' in 'a'.
	
mov b a
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a'.
	SWP				//Move 'a' to A.
	LDI HIGH[b]		//Get the address of 'b'.
	PSH
	LDI MEDH[b]
	PSH
	LDI MEDL[b]
	PSH
	LDI LOW[b]
	PSH
	SWP				//Move 'a' to B.
	ST				//Store 'a' in 'b'.
	
nop
	NOP
	
jmp #3 #2 #1 #0
	LDI #3			//Load address to jump to.
	PSH
	LDI #2
	PSH
	LDI #1
	PSH
	LDI #0
	PSH
	MOV				//Compare A to itself.
	CMP
	BR EQ			//Branch if equal (which it will be).
	
not a
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a' to A.
	SWP
	LDI F			//Invert 'a'.
	XOR
	MOV
	ST				//Store ~'a' back to 'a'.
	
neg a
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LDI 0			//Move 0 to A.
	SWP
	LD				//Load 'a'.
	SUB				//Subtract 'a' from 0. (Negate 'a'.)
	MOV
	ST				//Store -'a' back to 'a'.
	
inc a
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a'.
	SWP				//Add 1 to 'a'.
	LDI 1
	ADD
	MOV
	ST				//Store 'a' + 1 back to 'a'.
	
dec a
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a'.
	SWP				//Subtract 1 from 'a'.
	LDI 1
	SUB
	MOV
	ST				//Store 'a' - 1 back to 'a'.
	
addi a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a'.
	SWP				//Add # to 'a'.
	LDI #
	ADD
	MOV
	ST				//Store 'a' + # back to 'a'.
	
subi a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a'.
	SWP				//Subtract # from 'a'.
	LDI #
	SUB
	MOV
	ST				//Store 'a' - # back to 'a'.
	
andi a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD
	SWP
	LDI #
	AND
	MOV
	ST	
	
ori a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD
	SWP
	LDI #
	OR
	MOV
	ST	
	
xori a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD
	SWP
	LDI #
	XOR
	MOV
	ST	
	
getf	//Store flags in designated FLAG memory location.
	LDI HIGH[FLAG]
	PSH
	LDI MIDH[FLAG]
	PSH
	LDI MIDL[FLAG]
	PSH
	LDI LOW[FLAG]
	PSH
	SWF
	ST
	
putf	//Load flags from designated FLAG memory location.
	LDI HIGH[FLAG]
	PSH
	LDI MIDH[FLAG]
	PSH
	LDI MIDL[FLAG]
	PSH
	LDI LOW[FLAG]
	PSH
	LD
	SWF
	
xnori a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD
	SWP
	LDI #
	XOR
	LDI F
	XOR
	MOV
	ST	
	
cmpi a #
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a'.
	SWP				//Subtract # from 'a'.
	LDI #
	CMP
	getf			//Update flags.
	
test a
	LDI HIGH[a]		//Get the address of 'a'.
	PSH
	LDI MEDH[a]
	PSH
	LDI MEDL[a]
	PSH
	LDI LOW[a]
	PSH
	LD				//Load 'a'.
	SWP				//Subtract # from 'a'.
	LDI 0
	CMP
	getf			//Update flags.

Version 1.0

New processor goal: Create a small accumulator based 4-bit architecture that can emulate a memory-memory instruction set.

registers:
0	a
1	b
2	c
3	ar[0]

Instruction description:
0	ldi r #	ldi r #
1	psh		ar[n] -> ar[n + 1]
2	inc		ar++
3	add		a += b
4	sub		a -= b
5	and		a &= b
6	or		a |= b
7	xor		a ^= b
8	mov r r	r -> r
9	swf		a -> f; f -> a
#A	ld r	mem[ar] -> r
#B	st r	r -> mem[ar]
#C	cmp		a - b
#D	shr		a>>1 -> a
#E	nop
#F	br #

Instruction Classification:

Transfer
	ldi r #
	ld r
	st r
	mov r r
Math
	cmp
	sub
	add
	and
	or
	xor
	shr
Other
	nop
	br.c
	inc
	swf
	psh
	
Instruction list:
0	swf
1	cmp
2	sub
3	add
4	xor
5	or
6	and
7	shr
8	ldi
9	ld
#a	st
#b	mov
#c	psh
#d	inc
#e	br.
#f	nop
	
Op-code and register transfers:
0	swf
	mem[pc++] -> ir
	a -> f; f -> a
	
1	cmp
	mem[pc++] -> ir
	a - b
	
2	sub
	mem[pc++] -> ir
	a - b -> a
	
3	add
	mem[pc++] -> ir
	a + b -> a
	
4	xor
	mem[pc++] -> ir
	a ^ b -> a
	
5	or
	mem[pc++] -> ir
	a | b -> a
	
6	and
	mem[pc++] -> ir
	a & b -> a
	
7	shr
	mem[pc++] -> ir
	a >> 1 -> a
	
8	ldi
	mem[pc++] -> ir
	mem[pc++] -> rar
	mem[pc++] -> reg[rar[1:0]]
	
9	ld
	mem[pc++] -> ir
	mem[pc++] -> rar
	mem[ar] -> reg[rar[1:0]]
	
#a	st
	mem[pc++] -> ir
	mem[pc++] -> rar
	reg[rar[3:2]] -> mem[ar]
	
#b	mov
	mem[pc++] -> ir
	mem[pc++] -> rar
	reg[rar[3:2]] -> reg[rar[1:0]]
	
#c	psh
	mem[pc++] -> ir
	ar[n] -> ar[n+1]
	
#d	inc
	mem[pc++] -> ir
	ar++
	
#e	br.
	mem[pc++] -> ir
	~(f[mem[pc][2:1]] ^ mem[pc][0]) ? ar : pc + 1 -> pc;
	
#f	nop
	mem[pc++] -> ir

Macro types:

Letter: address of a memory location.
Number: a 4-bit constant.

Macros:
%lda #
*ldi a #
*mov b a
nop
*jmp ####
*not a
*neg a
*inc a
*dec a
*addi a #
*subi a #
*andi a #
*ori a #
*xori a #
%stf
%ldf
*xnori a #
*cmpi a #
*test a
*ijmp [a, a+1, a+2, a+3]
*add a b
*sub a b
*cmp a b
*and a b
*or a b
*xor a b
*xnor a b
*ld b a
*st b a
*imov a b

*Memory-memory operations (designed for high-level programming)
%Memory-register operations (designed for low-level programming)

lda a
	LDI AR HIGH[a]
	PSH
	LDI AR MEDH[a]
	PSH
	LDI AR MEDL[a]
	PSH
	LDI AR LOW[a]
	
nop
	NOP

ldi a #
	lda a
	LDI C #
	ST C
	
mov b a
	lda a
	LD C
	lda b
	ST C
	
jmp a
	lda a
	MOV B A
	CMP
	BR.Z
	
not a
	lda a
	LD A
	LDI B F
	XOR
	ST A
	
neg a
	lda a
	LD B
	LDI A 0
	SUB
	ST A
	
inc a
	lda a
	LD A
	LDI B 1
	ADD
	ST A
	
dec a
	lda a
	LD A
	LDI B 1
	SUB
	ST A
	
addi a #
	lda a
	LD A
	LDI B #
	ADD
	ST A
	
subi a #
	lda a
	LD A
	LDI B #
	SUB
	ST A
	
andi a #
	lda a
	LD A
	LDI B #
	AND
	ST A
	
ori a #
	lda a
	LD A
	LDI B #
	OR
	ST A
	
xori a #
	lda a
	LD A
	LDI B #
	XOR
	ST A
	
stf a
	lda a
	SWF
	ST A
	
ldf a
	lda a
	LD A
	SWF
	
xnori a #
	lda a
	LD A
	LDI B #
	XOR
	LDI B F
	XOR
	ST A
	
cmpi a #
	lda a
	LD A
	LDI B #
	SUB
	
test a
	lda a
	LD A
	LDI B 0
	SUB
	
ijmp [a+3 a+2 a+1 a]
	lda a
	LD A
	INC
	LD B
	INC
	LD C
	INC
	LD AR
	PSH
	MOV AR C
	PSH
	MOV AR B
	PSH
	MOV AR A
	MOV B A
	CMP
	BR.Z
	
add a b
	lda b
	LD B
	lda a
	LD A
	ADD
	ST A
	
sub a b
	lda b
	LD B
	lda a
	LD A
	SUB
	ST A
	
cmp a b
	lda b
	LD B
	lda a
	LD A
	SUB
	
and a b
	lda b
	LD B
	lda a
	LD A
	AND
	ST A
	
or a b
	lda b
	LD B
	lda a
	LD A
	OR
	ST A
	
xor a b
	lda b
	LD B
	lda a
	LD A
	XOR
	ST A
	
xnor a b
	lda b
	LD B
	lda a
	LD A
	XOR
	LDI B F
	XOR
	ST A
	
ld a [b+3 b+2 b+1 b]
	lda b
	LD A
	INC
	LD B
	INC
	LD C
	INC
	LD AR
	PSH
	MOV AR C
	PSH
	MOV AR B
	PSH
	MOV AR A
	LD A
	lda a
	ST A
	
st [a+3 a+2 a+1 a] b
	lda b
	LD A
	SWF
	lda a
	LD A
	INC
	LD B
	INC
	LD C
	INC
	LD AR
	PSH
	MOV AR C
	PSH
	MOV AR B
	PSH
	MOV AR A
	SWF
	ST A
	
imov [a+3 a+2 a+1 a] [b+3 b+2 b+1 b]
	lda b
	LD A
	INC
	LD B
	INC
	LD C
	INC
	LD AR
	PSH
	MOV AR C
	PSH
	MOV AR B
	PSH
	MOV AR A
	LD A
	SWF
	lda a
	LD A
	INC
	LD B
	INC
	LD C
	INC
	LD AR
	PSH
	MOV AR C
	PSH
	MOV AR B
	PSH
	MOV AR A
	SWF
	ST A